When power is initially applied to systems having electrical circuitry, various components of the system typically power up in an unknown state. After applying power, a reset signal may be applied to such components to reset them to a known state.
Of particular importance is when the system components should be reset. Resetting system components as soon as possible during the power up process is desirable for at least two reasons. First, to minimize time between application of power and when the system is functional, the reset should be initiated during the power up process. Second, by performing a reset before full power levels are achieved, hazardous conditions that could damage system components can be avoided.
In order to reduce the time required to bring the system up to full functionality from the time at which the power was first applied, the reset function is typically initiated during the power up process. Although the steady state output of a power supply might have a given nominal level, time is required for the steady state output levels to become available throughout the system when the power supply is first activated. Because initializing and resetting system components also takes some amount of time, the initialization and resetting process should preferably take place as soon as possible after power is initially applied to the system. This permits initialization and reset functions to execute concurrently or at least begin during the power up process. This in turn helps to minimize the total amount of time required for power up, initialization, and reset.
Failure to reset system components in a timely manner may result in catastrophic failure for the system. For example, in a computer system, buses are typically used to communicate data, address, and control information between various system components. These components usually include a bus driver to transform electrical signals from the component into voltage and current levels required for bus communication. Ideally the bus drivers operate in a tri-state mode during the power up process so that none of them are attempting to send conflicting signals on the bus. When the power is first applied, however, one bus driver may initialize to a state in which it attempts to drive one value onto the bus while a second driver is attempting to drive another value on the bus. These different values are physically represented by opposing electrical values. Thus one driver may be attempting to drive a voltage approaching available power supply levels onto the bus while another is attempting to drive the bus to a signal ground. This hazardous condition can permanently damage the bus, a component coupled to the bus, or one or more bus drivers. To avoid such an event, system components are typically reset to a known state before the power supply reaches full output levels. Thus avoiding a risk of catastrophic failure is another reason for resetting system components during the power-up process and not afterwards.
A power up reset circuit is used to provide a reset signal to system components. The system components respond by resetting themselves to a known state after receipt of the reset signal. Some components require at least some minimal power supply level so that they can be reset to a known state. This means that the reset signal will not be effective until the power supply reaches at least this minimal level. The reset signal should be provided, however, while the power available to the system is still relatively low in order to avoid hazardous conditions such as that provided in the example above. Furthermore, the reset signal should be removed at some point during the power up process so that system can proceed with any necessary initialization procedures after the reset.
FIG. 1 illustrates a block diagram for a system using a reset circuit. FIG. 2 illustrates timing and voltage relationship between VCC and a reset signal. Referring to FIG. 1 and FIG. 2, the power supply output is provided to system 100 at time 210 by closing switch 110. The power supply output transitions over a discrete period of time to the nominal operating voltage as illustrated by power supply voltage level 220. Closing switch 110 couples the power supply output to the various system components such as microprocessor 130. Switch 110 couples the power supply output to power up reset circuit 120. In one prior art power up reset circuit, the reset signal is generated upon or shortly after initial application of the power supply voltage. FIG. 2 illustrates reset signal 230 being asserted at time 212. The reset circuit is coupled to provide the reset signal to the various system components (e.g., microprocessor 130) that need it. The reset signal remains on (i.e., asserted) until the power supply has reached a predetermined level. At this predetermined level (i.e., 240), the reset circuit deasserts the reset signal. The predetermined level at which the reset signal transitions from one state to the other state is referred to as the trigger point or trip point. In accordance with goals of 1) minimizing the time required for power up, reset, and initialization; and 2) avoiding the risk of catastrophic failure; the reset signal should be asserted upon or shortly after power is turned on and the trigger point is typically set to be somewhere between the minimal power supply level required for resetting and the power supply level beyond which catastrophic failure may result.
One prior art power up reset circuit uses the threshold voltage (V.sub.t) of one or more transistors in order to set or determine the trigger point level. Such a power up reset circuit is described in U.S. Pat. No. 5,111,067 of Wong, et al. One disadvantage of this prior art circuitry is that the threshold voltages can permanently shift over the course of continued power up and power down cycles such that the trigger point moves. The shifting of the trigger point can cause a reset signal to be generated too soon, too late, or even not at all. Thus decreasing the sensitivity of a power up reset circuit to shifting threshold voltages is desirable.